Changeset 3881

Show
Ignore:
Timestamp:
12/17/08 18:50:08 (3 years ago)
Author:
proski
Message:

Create madwifi-free branch from madwifi-hal-0.10.5.6

HAL sources are copied from svn://svn.freebsd.org/base/projects/ath_hal
(revision 186240).

No changes to makefiles are made at this point.

Files:

Legend:

Unmodified
Added
Removed
Modified
Copied
Moved

  • madwifi/branches/madwifi-free

    • Property svn:mergeinfo set

  • madwifi/branches/madwifi-free/hal/ah.h

    r3698 r3881  
    1 /*- 
    2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros 
    3  * Communications, Inc.  All rights reserved. 
     1/* 
     2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 
     3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 
    44 * 
    5  * Redistribution and use in source and binary forms are permitted 
    6  * provided that the following conditions are met: 
    7  * 1. The materials contained herein are unmodified and are used 
    8  *    unmodified. 
    9  * 2. Redistributions of source code must retain the above copyright 
    10  *    notice, this list of conditions and the following NO 
    11  *    ''WARRANTY'' disclaimer below (''Disclaimer''), without 
    12  *    modification. 
    13  * 3. Redistributions in binary form must reproduce at minimum a 
    14  *    disclaimer similar to the Disclaimer below and any redistribution 
    15  *    must be conditioned upon including a substantially similar 
    16  *    Disclaimer requirement for further binary redistribution. 
    17  * 4. Neither the names of the above-listed copyright holders nor the 
    18  *    names of any contributors may be used to endorse or promote 
    19  *    product derived from this software without specific prior written 
    20  *    permission. 
     5 * Permission to use, copy, modify, and/or distribute this software for any 
     6 * purpose with or without fee is hereby granted, provided that the above 
     7 * copyright notice and this permission notice appear in all copies. 
    218 * 
    22  * NO WARRANTY 
    23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    24  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 
    26  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
    27  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 
    28  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 
    30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
    31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
    32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 
    33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
    34  * SUCH DAMAGES. 
     9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 
     10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 
     11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 
     12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 
     13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 
     14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 
     15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 
    3516 * 
    3617 * $Id$ 
    …… 
    4728 * reference as the first parameter. 
    4829 */ 
    49  
    50 /* 
    51  * Bus i/o type definitions.  We define a platform-independent 
    52  * set of types that are mapped to platform-dependent data for 
    53  * register read/write operations.  We use types that are large 
    54  * enough to hold a pointer; smaller data should fit and only 
    55  * require type coercion to work.  Larger data can be stored 
    56  * elsewhere and a reference passed for the bus tag and/or handle. 
    57  */ 
    58 typedef void* HAL_SOFTC;                /* pointer to driver/OS state */ 
    59 typedef void* HAL_BUS_TAG;              /* opaque bus i/o id tag */ 
    60 typedef void* HAL_BUS_HANDLE;           /* opaque bus i/o handle */ 
    6130 
    6231#include "ah_osdep.h" 
    …… 
    12392        HAL_CAP_MCAST_KEYSRCH   = 19,   /* hardware has multicast key search */ 
    12493        HAL_CAP_TSF_ADJUST      = 20,   /* hardware has beacon tsf adjust */ 
    125         HAL_CAP_XR             = 21,   /* hardware has XR support */ 
     94        /* 21 was HAL_CAP_XR */ 
    12695        HAL_CAP_WME_TKIPMIC     = 22,   /* hardware can support TKIP MIC when WMM is turned on */ 
    127         HAL_CAP_CHAN_HALFRATE  = 23,   /* hardware can support half rate channels */ 
    128         HAL_CAP_CHAN_QUARTERRATE = 24, /* hardware can support quarter rate channels */ 
     96        /* 23 was HAL_CAP_CHAN_HALFRATE */ 
     97        /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 
    12998        HAL_CAP_RFSILENT        = 25,   /* hardware has rfsilent support  */ 
    13099        HAL_CAP_TPC_ACK         = 26,   /* ack txpower with per-packet tpc */ 
    …… 
    134103        HAL_CAP_RXORN_FATAL     = 30,   /* HAL_INT_RXORN treated as fatal */ 
    135104        HAL_CAP_HT              = 31,   /* hardware can support HT */ 
    136         HAL_CAP_NUMTXCHAIN     = 32,   /* # TX chains supported */ 
    137         HAL_CAP_NUMRXCHAIN     = 33,   /* # RX chains supported */ 
     105        HAL_CAP_TX_CHAINMASK   = 32,   /* mask of TX chains supported */ 
     106        HAL_CAP_RX_CHAINMASK   = 33,   /* mask of RX chains supported */ 
    138107        HAL_CAP_RXTSTAMP_PREC   = 34,   /* rx desc tstamp precision (bits) */ 
     108        HAL_CAP_BB_HANG         = 35,   /* can baseband hang */ 
     109        HAL_CAP_MAC_HANG        = 36,   /* can MAC hang */ 
    139110} HAL_CAPABILITY_TYPE; 
    140111 
    …… 
    180151        HAL_WME_AC_VO   = 3,                    /* voice access category */ 
    181152        HAL_WME_UPSD    = 4,                    /* uplink power save */ 
    182         HAL_XR_DATA     = 5,                    /* uplink power save */ 
    183153} HAL_TX_QUEUE_SUBTYPE; 
    184154 
    …… 
    268238 
    269239typedef struct { 
    270         u_int32_t     tqi_ver;                /* hal TXQ version */ 
     240        uint32_t      tqi_ver;                /* hal TXQ version */ 
    271241        HAL_TX_QUEUE_SUBTYPE tqi_subtype;       /* subtype if applicable */ 
    272242        HAL_TX_QUEUE_FLAGS tqi_qflags;          /* flags (see above) */ 
    273         u_int32_t     tqi_priority;           /* (not used) */ 
    274         u_int32_t     tqi_aifs;               /* aifs */ 
    275         u_int32_t     tqi_cwmin;              /* cwMin */ 
    276         u_int32_t     tqi_cwmax;              /* cwMax */ 
    277         u_int16_t     tqi_shretry;            /* rts retry limit */ 
    278         u_int16_t     tqi_lgretry;            /* long retry limit (not used)*/ 
    279         u_int32_t     tqi_cbrPeriod;          /* CBR period (us) */ 
    280         u_int32_t     tqi_cbrOverflowLimit;   /* threshold for CBROVF int */ 
    281         u_int32_t     tqi_burstTime;          /* max burst duration (us) */ 
    282         u_int32_t     tqi_readyTime;          /* frame schedule time (us) */ 
    283         u_int32_t     tqi_compBuf;            /* comp buffer phys addr */ 
     243        uint32_t      tqi_priority;           /* (not used) */ 
     244        uint32_t      tqi_aifs;               /* aifs */ 
     245        uint32_t      tqi_cwmin;              /* cwMin */ 
     246        uint32_t      tqi_cwmax;              /* cwMax */ 
     247        uint16_t      tqi_shretry;            /* rts retry limit */ 
     248        uint16_t      tqi_lgretry;            /* long retry limit (not used)*/ 
     249        uint32_t      tqi_cbrPeriod;          /* CBR period (us) */ 
     250        uint32_t      tqi_cbrOverflowLimit;   /* threshold for CBROVF int */ 
     251        uint32_t      tqi_burstTime;          /* max burst duration (us) */ 
     252        uint32_t      tqi_readyTime;          /* frame schedule time (us) */ 
     253        uint32_t      tqi_compBuf;            /* comp buffer phys addr */ 
    284254} HAL_TXQ_INFO; 
    285255 
    …… 
    287257 
    288258/* token to use for aifs, cwmin, cwmax */ 
    289 #define HAL_TXQ_USEDEFAULT      ((u_int32_t) -1) 
     259#define HAL_TXQ_USEDEFAULT      ((uint32_t) -1) 
    290260 
    291261/* compression definitions */ 
    …… 
    320290        HAL_RX_FILTER_BEACON    = 0x00000010,   /* Allow beacon frames */ 
    321291        HAL_RX_FILTER_PROM      = 0x00000020,   /* Promiscuous mode */ 
    322         HAL_RX_FILTER_XRPOLL    = 0x00000040,   /* Allow XR poll frmae */ 
    323292        HAL_RX_FILTER_PROBEREQ  = 0x00000080,   /* Allow probe request frames */ 
    324293        HAL_RX_FILTER_PHYERR    = 0x00000100,   /* Allow phy errors */ 
    …… 
    363332        HAL_INT_GPIO    = 0x01000000, 
    364333        HAL_INT_CABEND  = 0x02000000,   /* Non-common mapping */ 
     334        HAL_INT_TSFOOR  = 0x04000000,   /* Non-common mapping */ 
    365335        HAL_INT_CST     = 0x10000000,   /* Non-common mapping */ 
    366336        HAL_INT_GTT     = 0x20000000,   /* Non-common mapping */ 
    …… 
    397367 */ 
    398368typedef struct { 
    399         u_int32_t     channelFlags;   /* see below */ 
    400         u_int16_t     channel;        /* setting in Mhz */ 
    401         u_int8_t      privFlags; 
     369        uint32_t      channelFlags;   /* see below */ 
     370        uint16_t      channel;        /* setting in Mhz */ 
     371        uint8_t               privFlags; 
    402372        int8_t          maxRegTxPower;  /* max regulatory tx power in dBm */ 
    403373        int8_t          maxTxPower;     /* max true tx power in 0.5 dBm */ 
    …… 
    414384#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */ 
    415385#define CHANNEL_DYN     0x00400 /* dynamic CCK-OFDM channel */ 
    416 #define CHANNEL_XR      0x00800 /* XR channel */ 
    417386#define CHANNEL_STURBO  0x02000 /* Static turbo, no 11a-only usage */ 
    418387#define CHANNEL_HALF    0x04000 /* Half rate channel */ 
    …… 
    442411#define CHANNEL_108G    (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 
    443412#define CHANNEL_108A    CHANNEL_T 
    444 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 
    445413#define CHANNEL_G_HT20          (CHANNEL_G|CHANNEL_HT20) 
    446414#define CHANNEL_A_HT20          (CHANNEL_A|CHANNEL_HT20) 
    …… 
    460428 
    461429typedef struct { 
    462         u_int32_t     ackrcv_bad; 
    463         u_int32_t     rts_bad; 
    464         u_int32_t     rts_good; 
    465         u_int32_t     fcs_bad; 
    466         u_int32_t     beacons; 
     430        uint32_t      ackrcv_bad; 
     431        uint32_t      rts_bad; 
     432        uint32_t      rts_good; 
     433        uint32_t      fcs_bad; 
     434        uint32_t      beacons; 
    467435} HAL_MIB_STATS; 
    468436 
    469 typedef u_int16_t HAL_CTRY_CODE;              /* country code */ 
    470 typedef u_int16_t HAL_REG_DOMAIN;             /* regulatory domain code */ 
     437typedef uint16_t HAL_CTRY_CODE;               /* country code */ 
     438typedef uint16_t HAL_REG_DOMAIN;              /* regulatory domain code */ 
    471439 
    472440enum { 
    …… 
    485453        HAL_MODE_11G    = 0x008,                /* XXX historical */ 
    486454#endif 
    487         HAL_MODE_108G   = 0x020,                /* 11a+Turbo channels */ 
    488         HAL_MODE_108A   = 0x040,                /* 11g+Turbo channels */ 
    489         HAL_MODE_XR     = 0x100,                /* XR channels */ 
    490         HAL_MODE_11A_HALF_RATE = 0x200,         /* 11A half rate channels */ 
    491         HAL_MODE_11A_QUARTER_RATE = 0x400,      /* 11A quarter rate channels */ 
     455        HAL_MODE_108G   = 0x020,                /* 11g+Turbo channels */ 
     456        HAL_MODE_108A   = 0x040,                /* 11a+Turbo channels */ 
     457        HAL_MODE_11A_HALF_RATE = 0x200,         /* 11a half width channels */ 
     458        HAL_MODE_11A_QUARTER_RATE = 0x400,      /* 11a quarter width channels */ 
     459        HAL_MODE_11G_HALF_RATE = 0x800,         /* 11g half width channels */ 
     460        HAL_MODE_11G_QUARTER_RATE = 0x1000,     /* 11g quarter width channels */ 
    492461        HAL_MODE_11NG_HT20      = 0x008000, 
    493462        HAL_MODE_11NA_HT20      = 0x010000, 
    …… 
    501470typedef struct { 
    502471        int             rateCount;              /* NB: for proper padding */ 
    503         u_int8_t      rateCodeToIndex[144];   /* back mapping */ 
     472        uint8_t               rateCodeToIndex[144];   /* back mapping */ 
    504473        struct { 
    505                 u_int8_t      valid;          /* valid for rate control use */ 
    506                 u_int8_t      phy;            /* CCK/OFDM/XR */ 
    507                 u_int32_t     rateKbps;       /* transfer rate in kbs */ 
    508                 u_int8_t      rateCode;       /* rate for h/w descriptors */ 
    509                 u_int8_t      shortPreamble;  /* mask for enabling short 
     474                uint8_t       valid;          /* valid for rate control use */ 
     475                uint8_t       phy;            /* CCK/OFDM/XR */ 
     476                uint32_t      rateKbps;       /* transfer rate in kbs */ 
     477                uint8_t               rateCode;       /* rate for h/w descriptors */ 
     478                uint8_t               shortPreamble;  /* mask for enabling short 
    510479                                                 * preamble in CCK rate code */ 
    511                 u_int8_t      dot11Rate;      /* value for supported rates 
     480                uint8_t               dot11Rate;      /* value for supported rates 
    512481                                                 * info element of MLME */ 
    513                 u_int8_t      controlRate;    /* index of next lower basic 
     482                uint8_t               controlRate;    /* index of next lower basic 
    514483                                                 * rate; used for dur. calcs */ 
    515                 u_int16_t     lpAckDuration;  /* long preamble ACK duration */ 
    516                 u_int16_t     spAckDuration;  /* short preamble ACK duration*/ 
     484                uint16_t      lpAckDuration;  /* long preamble ACK duration */ 
     485                uint16_t      spAckDuration;  /* short preamble ACK duration*/ 
    517486        } info[32]; 
    518487} HAL_RATE_TABLE; 
    …… 
    520489typedef struct { 
    521490        u_int           rs_count;               /* number of valid entries */ 
    522         u_int8_t      rs_rates[32];           /* rates */ 
     491        uint8_t       rs_rates[32];           /* rates */ 
    523492} HAL_RATE_SET; 
    524493 
    …… 
    583552 
    584553typedef struct { 
    585         u_int8_t      kv_type;                /* one of HAL_CIPHER */ 
    586         u_int8_t      kv_pad; 
    587         u_int16_t     kv_len;                 /* length in bits */ 
    588         u_int8_t      kv_val[16];             /* enough for 128-bit keys */ 
    589         u_int8_t      kv_mic[8];              /* TKIP MIC key */ 
    590         u_int8_t      kv_txmic[8];            /* TKIP TX MIC key (optional) */ 
     554        uint8_t               kv_type;                /* one of HAL_CIPHER */ 
     555        uint8_t               kv_pad; 
     556        uint16_t      kv_len;                 /* length in bits */ 
     557        uint8_t               kv_val[16];             /* enough for 128-bit keys */ 
     558        uint8_t               kv_mic[8];              /* TKIP MIC key */ 
     559        uint8_t               kv_txmic[8];            /* TKIP TX MIC key (optional) */ 
    591560} HAL_KEYVAL; 
    592561 
    …… 
    616585 */ 
    617586typedef struct { 
    618         u_int32_t     bs_nexttbtt;            /* next beacon in TU */ 
    619         u_int32_t     bs_nextdtim;            /* next DTIM in TU */ 
    620         u_int32_t     bs_intval;              /* beacon interval+flags */ 
     587        uint32_t      bs_nexttbtt;            /* next beacon in TU */ 
     588        uint32_t      bs_nextdtim;            /* next DTIM in TU */ 
     589        uint32_t      bs_intval;              /* beacon interval+flags */ 
    621590#define HAL_BEACON_PERIOD       0x0000ffff      /* beacon interval period */ 
    622591#define HAL_BEACON_ENA          0x00800000      /* beacon xmit enable */ 
    623592#define HAL_BEACON_RESET_TSF    0x01000000      /* clear TSF */ 
    624         u_int32_t     bs_dtimperiod; 
    625         u_int16_t     bs_cfpperiod;           /* CFP period in TU */ 
    626         u_int16_t     bs_cfpmaxduration;      /* max CFP duration in TU */ 
    627         u_int32_t     bs_cfpnext;             /* next CFP in TU */ 
    628         u_int16_t     bs_timoffset;           /* byte offset to TIM bitmap */ 
    629         u_int16_t     bs_bmissthreshold;      /* beacon miss threshold */ 
    630         u_int32_t     bs_sleepduration;       /* max sleep duration */ 
     593        uint32_t      bs_dtimperiod; 
     594        uint16_t      bs_cfpperiod;           /* CFP period in TU */ 
     595        uint16_t      bs_cfpmaxduration;      /* max CFP duration in TU */ 
     596        uint32_t      bs_cfpnext;             /* next CFP in TU */ 
     597        uint16_t      bs_timoffset;           /* byte offset to TIM bitmap */ 
     598        uint16_t      bs_bmissthreshold;      /* beacon miss threshold */ 
     599        uint32_t      bs_sleepduration;       /* max sleep duration */ 
    631600} HAL_BEACON_STATE; 
    632601 
    …… 
    636605 */ 
    637606typedef struct { 
    638         u_int32_t     bt_intval;              /* beacon interval+flags */ 
    639         u_int32_t     bt_nexttbtt;            /* next beacon in TU */ 
    640         u_int32_t     bt_nextatim;            /* next ATIM in TU */ 
    641         u_int32_t     bt_nextdba;             /* next DBA in 1/8th TU */ 
    642         u_int32_t     bt_nextswba;            /* next SWBA in 1/8th TU */ 
    643         u_int32_t     bt_flags;               /* timer enables */ 
     607        uint32_t      bt_intval;              /* beacon interval+flags */ 
     608        uint32_t      bt_nexttbtt;            /* next beacon in TU */ 
     609        uint32_t      bt_nextatim;            /* next ATIM in TU */ 
     610        uint32_t      bt_nextdba;             /* next DBA in 1/8th TU */ 
     611        uint32_t      bt_nextswba;            /* next SWBA in 1/8th TU */ 
     612        uint32_t      bt_flags;               /* timer enables */ 
    644613#define HAL_BEACON_TBTT_EN      0x00000001 
    645614#define HAL_BEACON_DBA_EN       0x00000002 
    …… 
    652621 */ 
    653622typedef struct { 
    654         u_int32_t     ns_avgbrssi;    /* average beacon rssi */ 
    655         u_int32_t     ns_avgrssi;     /* average data rssi */ 
    656         u_int32_t     ns_avgtxrssi;   /* average tx rssi */ 
     623        uint32_t      ns_avgbrssi;    /* average beacon rssi */ 
     624        uint32_t      ns_avgrssi;     /* average data rssi */ 
     625        uint32_t      ns_avgtxrssi;   /* average tx rssi */ 
    657626} HAL_NODE_STATS; 
    658627 
    …… 
    674643 */ 
    675644struct ath_hal { 
    676         u_int32_t     ah_magic;       /* consistency check magic number */ 
    677         u_int32_t     ah_abi;         /* HAL ABI version */ 
    678 #define HAL_ABI_VERSION 0x08052700    /* YYMMDDnn */ 
    679         u_int16_t     ah_devid;       /* PCI device ID */ 
    680         u_int16_t     ah_subvendorid; /* PCI subvendor ID */ 
     645        uint32_t      ah_magic;       /* consistency check magic number */ 
     646        uint32_t      ah_abi;         /* HAL ABI version */ 
     647#define HAL_ABI_VERSION 0x08112800    /* YYMMDDnn */ 
     648        uint16_t      ah_devid;       /* PCI device ID */ 
     649        uint16_t      ah_subvendorid; /* PCI subvendor ID */ 
    681650        HAL_SOFTC       ah_sc;          /* back pointer to driver/os state */ 
    682651        HAL_BUS_TAG     ah_st;          /* params for register r+w */ 
    …… 
    684653        HAL_CTRY_CODE   ah_countryCode; 
    685654 
    686         u_int32_t     ah_macVersion;  /* MAC version id */ 
    687         u_int16_t     ah_macRev;      /* MAC revision */ 
    688         u_int16_t     ah_phyRev;      /* PHY revision */ 
     655        uint32_t      ah_macVersion;  /* MAC version id */ 
     656        uint16_t      ah_macRev;      /* MAC revision */ 
     657        uint16_t      ah_phyRev;      /* PHY revision */ 
    689658        /* NB: when only one radio is present the rev is in 5Ghz */ 
    690         u_int16_t     ah_analog5GhzRev;/* 5GHz radio revision */ 
    691         u_int16_t     ah_analog2GhzRev;/* 2GHz radio revision */ 
     659        uint16_t      ah_analog5GhzRev;/* 5GHz radio revision */ 
     660        uint16_t      ah_analog2GhzRev;/* 2GHz radio revision */ 
    692661 
    693662        const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 
    …… 
    702671        HAL_BOOL  __ahdecl(*ah_disable)(struct ath_hal *); 
    703672        void      __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 
    704         HAL_BOOL  __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *); 
    705         HAL_BOOL  __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t); 
    706  
    707         /* DFS support */ 
    708         HAL_BOOL  __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 
     673        HAL_BOOL  __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, 
     674                        HAL_BOOL *); 
     675        HAL_BOOL  __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *, 
     676                        u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); 
     677        HAL_BOOL  __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *); 
     678        HAL_BOOL  __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 
    709679 
    710680        /* Transmit functions */ 
    …… 
    719689        HAL_BOOL  __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 
    720690        HAL_BOOL  __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 
    721         u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 
    722         HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp); 
    723         u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 
     691        uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 
     692        HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 
     693        uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 
    724694        HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 
    725695        HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 
    …… 
    741711        HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 
    742712                                struct ath_desc *, struct ath_tx_status *); 
    743         void       __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *); 
     713        void       __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 
    744714        void       __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 
    745715 
    746716        /* Receive Functions */ 
    747         u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 
    748         void      __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp); 
     717        uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 
     718        void      __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 
    749719        void      __ahdecl(*ah_enableReceive)(struct ath_hal*); 
    750720        HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 
    …… 
    752722        void      __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 
    753723        void      __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 
    754                                 u_int32_t filter0, u_int32_t filter1); 
     724                                uint32_t filter0, uint32_t filter1); 
    755725        HAL_BOOL  __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 
    756                                 u_int32_t index); 
     726                                uint32_t index); 
    757727        HAL_BOOL  __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 
    758                                 u_int32_t index); 
    759         u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 
    760         void      __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t); 
     728                                uint32_t index); 
     729        uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 
     730        void      __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 
    761731        HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 
    762                                 u_int32_t size, u_int flags); 
     732                                uint32_t size, u_int flags); 
    763733        HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 
    764                                 struct ath_desc *, u_int32_t phyAddr, 
    765                                 struct ath_desc *next, u_int64_t tsf, 
     734                                struct ath_desc *, uint32_t phyAddr, 
     735                                struct ath_desc *next, uint64_t tsf, 
    766736                                struct ath_rx_status *); 
    767737        void      __ahdecl(*ah_rxMonitor)(struct ath_hal *, 
    …… 
    772742        /* Misc Functions */ 
    773743        HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 
    774                                 HAL_CAPABILITY_TYPE, u_int32_t capability, 
    775                                 u_int32_t *result); 
     744                                HAL_CAPABILITY_TYPE, uint32_t capability, 
     745                                uint32_t *result); 
    776746        HAL_BOOL   __ahdecl(*ah_setCapability)(struct ath_hal *, 
    777                                 HAL_CAPABILITY_TYPE, u_int32_t capability, 
    778                                 u_int32_t setting, HAL_STATUS *); 
     747                                HAL_CAPABILITY_TYPE, uint32_t capability, 
     748                                uint32_t setting, HAL_STATUS *); 
    779749        HAL_BOOL   __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 
    780                                 const void *args, u_int32_t argsize, 
    781                                 void **result, u_int32_t *resultsize); 
    782         void      __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *); 
    783         HAL_BOOL  __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*); 
    784         void      __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *); 
    785         HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t*); 
     750                                const void *args, uint32_t argsize, 
     751                                void **result, uint32_t *resultsize); 
     752        void      __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 
     753        HAL_BOOL  __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 
     754        void      __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 
     755        HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 
    786756        HAL_BOOL  __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 
    787                                 u_int16_t, HAL_STATUS *); 
     757                                uint16_t, HAL_STATUS *); 
    788758        void      __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 
    789759        void      __ahdecl(*ah_writeAssocid)(struct ath_hal*, 
    790                                 const u_int8_t *bssid, u_int16_t assocId); 
    791         HAL_BOOL  __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio); 
    792         HAL_BOOL  __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio); 
    793         u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio); 
     760                                const uint8_t *bssid, uint16_t assocId); 
     761        HAL_BOOL  __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 
     762        HAL_BOOL  __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 
     763        uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 
    794764        HAL_BOOL  __ahdecl(*ah_gpioSet)(struct ath_hal *, 
    795                                 u_int32_t gpio, u_int32_t val); 
    796         void      __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t); 
    797         u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 
    798         u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 
     765                                uint32_t gpio, uint32_t val); 
     766        void      __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 
     767        uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 
     768        uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 
    799769        void      __ahdecl(*ah_resetTsf)(struct ath_hal*); 
    800770        HAL_BOOL  __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 
    …… 
    817787        HAL_BOOL  __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 
    818788        u_int     __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 
    819         HAL_BOOL  __ahdecl(*ah_setDecompMask)(struct ath_hal*, u_int16_t, int); 
    820         void      __ahdecl(*ah_setCoverageClass)(struct ath_hal*, u_int8_t, int); 
     789        HAL_BOOL  __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 
     790        void      __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 
    821791 
    822792        /* Key Cache Functions */ 
    823         u_int32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 
    824         HAL_BOOL  __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t); 
     793        uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 
     794        HAL_BOOL  __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 
    825795        HAL_BOOL  __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 
    826                                 u_int16_t); 
     796                                uint16_t); 
    827797        HAL_BOOL  __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 
    828                                 u_int16_t, const HAL_KEYVAL *, 
    829                                 const u_int8_t *, int); 
     798                                uint16_t, const HAL_KEYVAL *, 
     799                                const uint8_t *, int); 
    830800        HAL_BOOL  __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 
    831                                 u_int16_t, const u_int8_t *); 
     801                                uint16_t, const uint8_t *); 
    832802 
    833803        /* Power Management Functions */ 
    …… 
    842812        /* NB: deprecated, use ah_setBeaconTimers instead */ 
    843813        void      __ahdecl(*ah_beaconInit)(struct ath_hal *, 
    844                                 u_int32_t nexttbtt, u_int32_t intval); 
     814                                uint32_t nexttbtt, uint32_t intval); 
    845815        void      __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 
    846816                                const HAL_BEACON_STATE *); 
    …… 
    859829 * AH_NULL is returned if the ID's do not describe Atheros hardware. 
    860830 */ 
    861 extern  const char *__ahdecl ath_hal_probe(u_int16_t vendorid, u_int16_t devid); 
     831extern  const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 
    862832 
    863833/* 
    …… 
    874844 * be returned if the status parameter is non-zero. 
    875845 */ 
    876 extern  struct ath_hal * __ahdecl ath_hal_attach(u_int16_t devid, HAL_SOFTC, 
     846extern  struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 
    877847                HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status); 
    878  
    879 /* 
    880  * Set the Vendor ID for Vendor SKU's which can modify the 
    881  * channel properties returned by ath_hal_init_channels. 
    882  */ 
    883 extern  HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t ); 
    884848 
    885849/* 
    …… 
    896860extern  HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *, 
    897861                HAL_CHANNEL *chans, u_int maxchans, u_int *nchans, 
    898                 u_int8_t *regclassids, u_int maxregids, u_int *nregids, 
     862                uint8_t *regclassids, u_int maxregids, u_int *nregids, 
    899863                HAL_CTRY_CODE cc, u_int modeSelect, 
    900864                HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); 
    …… 
    914878 * Calculate the transmit duration of a frame. 
    915879 */ 
    916 extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 
    917                 const HAL_RATE_TABLE *rates, u_int32_t frameLen, 
    918                 u_int16_t rateix, HAL_BOOL shortPreamble); 
     880extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 
     881                const HAL_RATE_TABLE *rates, uint32_t frameLen, 
     882                uint16_t rateix, HAL_BOOL shortPreamble); 
    919883 
    920884/* 
    …… 
    933897 */ 
    934898extern  int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags); 
    935  
    936 /* 
    937  * Return a version string for the HAL release. 
    938  */ 
    939 extern  char ath_hal_version[]; 
    940 /* 
    941  * Return a NULL-terminated array of build/configuration options. 
    942  */ 
    943 extern  const char* ath_hal_buildopts[]; 
    944899#endif /* _ATH_AH_H_ */ 

  • madwifi/branches/madwifi-free/hal/ah_desc.h

    r3698 r3881  
    1 /*- 
    2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros 
    3  * Communications, Inc.  All rights reserved. 
    4  * 
    5  * Redistribution and use in source and binary forms are permitted 
    6  * provided that the following conditions are met: 
    7  * 1. The materials contained herein are unmodified and are used 
    8  *    unmodified. 
    9  * 2. Redistributions of source code must retain the above copyright 
    10  *    notice, this list of conditions and the following NO 
    11  *    ''WARRANTY'' disclaimer below (''Disclaimer''), without 
    12  *    modification. 
    13  * 3. Redistributions in binary form must reproduce at minimum a 
    14  *    disclaimer similar to the Disclaimer below and any redistribution 
    15  *    must be conditioned upon including a substantially similar 
    16  *    Disclaimer requirement for further binary redistribution. 
    17  * 4. Neither the names of the above-listed copyright holders nor the 
    18  *    names of any contributors may be used to endorse or promote 
    19  *    product derived from this software without specific prior written 
    20  *    permission. 
    21  * 
    22  * NO WARRANTY 
    23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    24  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 
    26  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
    27  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 
    28  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 
    30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
    31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
    32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 
    33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
    34  * SUCH DAMAGES. 
     1/* 
     2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 
     3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 
     4 * 
     5 * Permission to use, copy, modify, and/or distribute this software for any 
     6 * purpose with or without fee is hereby granted, provided that the above 
     7 * copyright notice and this permission notice appear in all copies. 
     8 * 
     9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 
     10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 
     11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 
     12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 
     13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 
     14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 
     15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 
    3516 * 
    3617 * $Id$ 
    …… 
    5233 */ 
    5334struct ath_tx_status { 
    54         u_int16_t     ts_seqnum;      /* h/w assigned sequence number */ 
    55         u_int16_t     ts_tstamp;      /* h/w assigned timestamp */ 
    56         u_int8_t      ts_status;      /* frame status, 0 => xmit ok */ 
    57         u_int8_t      ts_rate;        /* h/w transmit rate index */ 
     35        uint16_t      ts_seqnum;      /* h/w assigned sequence number */ 
     36        uint16_t      ts_tstamp;      /* h/w assigned timestamp */ 
     37        uint8_t               ts_status;      /* frame status, 0 => xmit ok */ 
     38        uint8_t               ts_rate;        /* h/w transmit rate index */ 
    5839#define HAL_TXSTAT_ALTRATE      0x80    /* alternate xmit rate used */ 
    5940        int8_t          ts_rssi;        /* tx ack RSSI */ 
    60         u_int8_t      ts_shortretry;  /* # short retries */ 
    61         u_int8_t      ts_longretry;   /* # long retries */ 
    62         u_int8_t      ts_virtcol;     /* virtual collision count */ 
    63         u_int8_t      ts_antenna;     /* antenna information */ 
    64         u_int8_t      ts_finaltsi;    /* final transmit series index */ 
     41        uint8_t               ts_shortretry;  /* # short retries */ 
     42        uint8_t               ts_longretry;   /* # long retries */ 
     43        uint8_t               ts_virtcol;     /* virtual collision count */ 
     44        uint8_t               ts_antenna;     /* antenna information */ 
     45        uint8_t               ts_finaltsi;    /* final transmit series index */ 
    6546#ifdef AH_SUPPORT_AR5416 
    6647                                        /* 802.11n status */ 
    67         u_int8_t      ts_flags;       /* misc flags */ 
     48        uint8_t       ts_flags;       /* misc flags */ 
    6849        int8_t          ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 
    6950        int8_t          ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 
    7051/* #define ts_rssi ts_rssi_combined */ 
    71         u_int32_t     ts_ba_low;      /* blockack bitmap low */ 
    72         u_int32_t     ts_ba_high;     /* blockack bitmap high */ 
    73         u_int32_t     ts_evm0;        /* evm bytes */ 
    74         u_int32_t     ts_evm1; 
    75         u_int32_t     ts_evm2; 
     52        uint32_t      ts_ba_low;      /* blockack bitmap low */ 
     53        uint32_t      ts_ba_high;     /* blockack bitmap high */ 
     54        uint32_t      ts_evm0;        /* evm bytes */ 
     55        uint32_t      ts_evm1; 
     56        uint32_t      ts_evm2; 
    7657#endif /* AH_SUPPORT_AR5416 */ 
    7758}; 
    …… 
    8263#define HAL_TXERR_FIFO          0x04    /* fifo underrun */ 
    8364#define HAL_TXERR_XTXOP         0x08    /* txop exceeded */ 
    84 #define HAL_TXERR_DESC_CFG_ERR  0x10    /* Error in 20/40 desc config */ 
    85 #define HAL_TXERR_DATA_UNDERRUN 0x20    /* Tx buffer underrun */ 
    86 #define HAL_TXERR_DELIM_UNDERRUN 0x40   /* Tx delimiter underrun */ 
     65#define HAL_TXERR_TIMER_EXPIRED 0x10    /* Tx timer expired */ 
    8766 
    8867/* bits found in ts_flags */ 
    8968#define HAL_TX_BA               0x01    /* Block Ack seen */ 
    9069#define HAL_TX_AGGR             0x02    /* Aggregate */  
     70#define HAL_TX_DESC_CFG_ERR     0x10    /* Error in 20/40 desc config */ 
     71#define HAL_TX_DATA_UNDERRUN    0x20    /* Tx buffer underrun */ 
     72#define HAL_TX_DELIM_UNDERRUN   0x40    /* Tx delimiter underrun */ 
    9173 
    9274/* 
    …… 
    11395 */ 
    11496struct ath_rx_status { 
    115         u_int16_t     rs_datalen;     /* rx frame length */ 
    116         u_int8_t      rs_status;      /* rx status, 0 => recv ok */ 
    117         u_int8_t      rs_phyerr;      /* phy error code */ 
     97        uint16_t      rs_datalen;     /* rx frame length */ 
     98        uint8_t               rs_status;      /* rx status, 0 => recv ok */ 
     99        uint8_t               rs_phyerr;      /* phy error code */ 
    118100        int8_t          rs_rssi;        /* rx frame RSSI (combined for 11n) */ 
    119         u_int8_t      rs_keyix;       /* key cache index */ 
    120         u_int8_t      rs_rate;        /* h/w receive rate index */ 
    121         u_int8_t      rs_more;        /* more descriptors follow */ 
    122         u_int32_t     rs_tstamp;      /* h/w assigned timestamp */ 
    123         u_int32_t     rs_antenna;     /* antenna information */ 
     101        uint8_t               rs_keyix;       /* key cache index */ 
     102        uint8_t               rs_rate;        /* h/w receive rate index */ 
     103        uint8_t               rs_more;        /* more descriptors follow */ 
     104        uint32_t      rs_tstamp;      /* h/w assigned timestamp */ 
     105        uint32_t      rs_antenna;     /* antenna information */ 
    124106#ifdef AH_SUPPORT_AR5416 
    125107                                        /* 802.11n status */ 
    126108        int8_t          rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 
    127109        int8_t          rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 
    128         u_int8_t      rs_isaggr;      /* is part of the aggregate */ 
    129         u_int8_t      rs_moreaggr;    /* more frames in aggr to follow */ 
    130         u_int8_t      rs_num_delims;  /* number of delims in aggr */ 
    131         u_int8_t      rs_flags;       /* misc flags */ 
    132         u_int32_t     rs_evm0;        /* evm bytes */ 
    133         u_int32_t     rs_evm1; 
    134         u_int32_t     rs_evm2;         
     110        uint8_t               rs_isaggr;      /* is part of the aggregate */ 
     111        uint8_t               rs_moreaggr;    /* more frames in aggr to follow */ 
     112        uint8_t               rs_num_delims;  /* number of delims in aggr */ 
     113        uint8_t               rs_flags;       /* misc flags */ 
     114        uint32_t      rs_evm0;        /* evm bytes */ 
     115        uint32_t      rs_evm1; 
     116        uint32_t      rs_evm2;         
    135117#endif /* AH_SUPPORT_AR5416 */ 
    136118}; 
    …… 
    151133#define HAL_RX_DELIM_CRC_POST   0x20    /* crc error in delim after */ 
    152134#define HAL_RX_DECRYPT_BUSY     0x40    /* decrypt was too slow */ 
    153 #define HAL_RX_DUP_FRAME       0x80    /* Dup frame rx'd on control channel */ 
     135#define HAL_RX_HI_RX_CHAIN     0x80    /* SM power save: hi Rx chain control */ 
    154136 
    155137enum { 
    …… 
    178160 
    179161/* value found in rs_keyix to mark invalid entries */ 
    180 #define HAL_RXKEYIX_INVALID     ((u_int8_t) -1) 
     162#define HAL_RXKEYIX_INVALID     ((uint8_t) -1) 
    181163/* value used to specify no encryption key for xmit */ 
    182164#define HAL_TXKEYIX_INVALID     ((u_int) -1) 
    …… 
    204186         * should not touch those elements marked opaque. 
    205187         */ 
    206         u_int32_t     ds_link;        /* phys address of next descriptor */ 
    207         u_int32_t     ds_data;        /* phys address of data buffer */ 
    208         u_int32_t     ds_ctl0;        /* opaque DMA control 0 */ 
    209         u_int32_t     ds_ctl1;        /* opaque DMA control 1 */ 
    210         u_int32_t     ds_hw[HAL_DESC_HW_SIZE];        /* opaque h/w region */ 
     188        uint32_t      ds_link;        /* phys address of next descriptor */ 
     189        uint32_t      ds_data;        /* phys address of data buffer */ 
     190        uint32_t      ds_ctl0;        /* opaque DMA control 0 */ 
     191        uint32_t      ds_ctl1;        /* opaque DMA control 1 */ 
     192        uint32_t      ds_hw[HAL_DESC_HW_SIZE];        /* opaque h/w region */ 
    211193}; 
    212194 

  • madwifi/branches/madwifi-free/hal/ah_devid.h

    r3698 r3881  
    1 /*- 
    2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros 
    3  * Communications, Inc.  All rights reserved. 
     1/* 
     2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 
     3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 
    44 * 
    5  * Redistribution and use in source and binary forms are permitted 
    6  * provided that the following conditions are met: 
    7  * 1. The materials contained herein are unmodified and are used 
    8  *    unmodified. 
    9  * 2. Redistributions of source code must retain the above copyright 
    10  *    notice, this list of conditions and the following NO 
    11  *    ''WARRANTY'' disclaimer below (''Disclaimer''), without 
    12  *    modification. 
    13  * 3. Redistributions in binary form must reproduce at minimum a 
    14  *    disclaimer similar to the Disclaimer below and any redistribution 
    15  *    must be conditioned upon including a substantially similar 
    16  *    Disclaimer requirement for further binary redistribution. 
    17  * 4. Neither the names of the above-listed copyright holders nor the 
    18  *    names of any contributors may be used to endorse or promote 
    19  *    product derived from this software without specific prior written 
    20  *    permission. 
     5 * Permission to use, copy, modify, and/or distribute this software for any 
     6 * purpose with or without fee is hereby granted, provided that the above 
     7 * copyright notice and this permission notice appear in all copies. 
    218 * 
    22  * NO WARRANTY 
    23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    24  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 
    26  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
    27  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 
    28  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 
    30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
    31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
    32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 
    33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
    34  * SUCH DAMAGES. 
     9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 
     10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 
     11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 
     12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 
     13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 
     14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 
     15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 
    3516 * 
    3617 * $Id$ 
    …… 
    9172#define AR5213_SREV_REG         0x4020 
    9273 
    93 /* AR5416  */ 
    94 #define AR5416_DEVID_EMU_PCI    0xff1d          /* PCI Owl Emulation*/ 
    95 #define AR5416_DEVID_EMU_PCIE   0xff1c          /* PCIe Owl Emulation*/ 
    96 #define AR5416_DEVID            0x0023          /* PCI (MB/CB) */ 
    97 #define AR5418_DEVID            0x0024          /* PCI Express (XB) */ 
     74/* AR5416 compatible devid's  */ 
     75#define AR5416_DEVID_PCI        0x0023          /* AR5416 PCI (MB/CB) Owl */ 
     76#define AR5416_DEVID_PCIE       0x0024          /* AR5416 PCI-E (XB) Owl */ 
     77#define AR9160_DEVID_PCI        0x0027          /* AR9160 PCI Sowl */ 
     78#define AR9280_DEVID_PCI        0x0029          /* AR9280 PCI Merlin */ 
     79#define AR9280_DEVID_PCIE       0x002a          /* AR9280 PCI-E Merlin */ 
     80#define AR9285_DEVID_PCIE       0x002b          /* AR9285 PCI-E Kite */ 
    9881 
    9982#define AR_SUBVENDOR_ID_NOG     0x0e11          /* No 11G subvendor ID */ 

  • madwifi/branches/madwifi-free/hal/ah_soc.h

    r3698 r3881  
    1 /*- 
    2  * Copyright (c) 2006-2008 Sam Leffler, Errno Consulting, Atheros 
    3  * Communications, Inc.  All rights reserved. 
     1/* 
     2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 
     3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 
    44 * 
    5  * Redistribution and use in source and binary forms are permitted 
    6  * provided that the following conditions are met: 
    7  * 1. The materials contained herein are unmodified and are used 
    8  *    unmodified. 
    9  * 2. Redistributions of source code must retain the above copyright 
    10  *    notice, this list of conditions and the following NO 
    11  *    ''WARRANTY'' disclaimer below (''Disclaimer''), without 
    12  *    modification. 
    13  * 3. Redistributions in binary form must reproduce at minimum a 
    14  *    disclaimer similar to the Disclaimer below and any redistribution 
    15  *    must be conditioned upon including a substantially similar 
    16  *    Disclaimer requirement for further binary redistribution. 
    17  * 4. Neither the names of the above-listed copyright holders nor the 
    18  *    names of any contributors may be used to endorse or promote 
    19  *    product derived from this software without specific prior written 
    20  *    permission. 
     5 * Permission to use, copy, modify, and/or distribute this software for any 
     6 * purpose with or without fee is hereby granted, provided that the above 
     7 * copyright notice and this permission notice appear in all copies. 
    218 * 
    22  * NO WARRANTY 
    23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    24  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 
    26  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
    27  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 
    28  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 
    30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
    31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
    32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 
    33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
    34  * SUCH DAMAGES. 
     9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 
     10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 
     11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 
     12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 
     13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 
     14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 
     15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 
    3516 * 
    36  * $Id: //depot/sw/branches/sam_hal/ah_soc.h#4 $ 
     17 * $Id: ah_soc.h,v 1.4 2008/11/10 04:08:00 sam Exp $ 
    3718 */ 
    3819#ifndef _ATH_AH_SOC_H_ 
    …… 
    5132 */ 
    5233struct ar531x_boarddata { 
    53         u_int32_t magic;             /* board data is valid */ 
     34        uint32_t magic;             /* board data is valid */ 
    5435#define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */ 
    55         u_int16_t cksum;             /* checksum (starting with BD_REV 2) */ 
    56         u_int16_t rev;               /* revision of this struct */ 
     36        uint16_t cksum;             /* checksum (starting with BD_REV 2) */ 
     37        uint16_t rev;               /* revision of this struct */ 
    5738#define BD_REV  4 
    5839        char   boardName[64];        /* Name of board */ 
    59         u_int16_t major;             /* Board major number */ 
    60         u_int16_t minor;             /* Board minor number */ 
    61         u_int32_t config;            /* Board configuration */ 
     40        uint16_t major;             /* Board major number */ 
     41        uint16_t minor;             /* Board minor number */ 
     42        uint32_t config;            /* Board configuration */ 
    6243#define BD_ENET0        0x00000001   /* ENET0 is stuffed */ 
    6344#define BD_ENET1        0x00000002   /* ENET1 is stuffed */ 
    …… 
    7859#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */ 
    7960#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */ 
    80         u_int16_t resetConfigGpio;   /* Reset factory GPIO pin */ 
    81         u_int16_t sysLedGpio;        /* System LED GPIO pin */ 
     61        uint16_t resetConfigGpio;   /* Reset factory GPIO pin */ 
     62        uint16_t sysLedGpio;        /* System LED GPIO pin */ 
    8263         
    83         u_int32_t cpuFreq;           /* CPU core frequency in Hz */ 
    84         u_int32_t sysFreq;           /* System frequency in Hz */ 
    85         u_int32_t cntFreq;           /* Calculated C0_COUNT frequency */ 
     64        uint32_t cpuFreq;           /* CPU core frequency in Hz */ 
     65        uint32_t sysFreq;           /* System frequency in Hz */ 
     66        uint32_t cntFreq;           /* Calculated C0_COUNT frequency */ 
    8667         
    87         u_int8_t  wlan0Mac[6]; 
    88         u_int8_t  enet0Mac[6]; 
    89         u_int8_t  enet1Mac[6]; 
     68        uint8_t  wlan0Mac[6]; 
     69        uint8_t  enet0Mac[6]; 
     70        uint8_t  enet1Mac[6]; 
    9071         
    91         u_int16_t pciId;             /* Pseudo PCIID for common code */ 
    92         u_int16_t memCap;            /* cap bank1 in MB */ 
     72        uint16_t pciId;             /* Pseudo PCIID for common code */ 
     73        uint16_t memCap;            /* cap bank1 in MB */ 
    9374         
    9475        /* version 3 */ 
    95         u_int8_t  wlan1Mac[6];       /* (ar5212) */ 
     76        uint8_t  wlan1Mac[6];       /* (ar5212) */ 
    9677}; 
    9778